SigmaRAM™ Fact Sheet
Overview:
Founded in July 1999, the SigmaRAM Consortium is an industry group of five leading SRAM companies that collaborated to
set open standards for a new breed of high-speed synchronous SRAMs. The consortium succeeded in developing the
industry's first open SRAM standard targeted specifically for the networking and telecommunications markets.
Approved by JEDEC, the SigmaRAM SRAM standard allows all SRAM manufacturers the opportunity to develop compatible
devices.
Member companies include GSI Technology, Integrated Silicon Solution Inc., Mitsubishi Electric Corporation, Sony
Electronics Inc. and Toshiba Corporation.
Technology and Benefits:
The rapidly expanding Internet economy is constantly demanding higher throughput from today's network and
telecommunications infrastructure. As a result, the pressure on system hardware such as switches, routers and
multiservice aggregators continues to mount. Responding to this need, the SigmaRAM Consortium has developed
worldwide-standardized specifications, pinouts, packages and products from 18Mb to 144Mb densities. This new
generation of ultra-fast SRAM enables system hardware to perform at maximum speed with real-time buffering. It enables
the capturing of multimedia data at wire speed at any point within the Internet. The SigmaRAM SRAM technology delivers
a unique solution that benefits OEMs through price/performance, amortized use of the same infrastructure for the next
four generations of SRAM, more functional options and density scalability. OEMs will also benefit from the open
standard and multiple-sourcing business model.
Architecture:
SigmaRAM devices come in two architectures — common I/O and separate I/O. They offer the widest data bus of 72
bits in the common I/O Single Data Rate architecture, and are the first to offer 36 bits in the separate I/O
architecture.
333MHz SigmaRAM devices are capable of sustaining up to 24Gb/s with entirely random addressing. Common I/O versions
share one data bus, yet incur no penalty when alternating between reads and writes. Separate I/O versions feature
independently optimized read and write buses. Both variations offer Double Data Rate architectures that can sustain
similar throughput with fewer pins.
Consortium members will begin sampling common I/O SigmaRAM SRAM devices beginning with an 18Mb version in Q4 2001.
Devices based on the separate I/O architecture are expected to be available at the end of the year.
Features:
- LVCMOS or HSTL interface on common I/O;
- HSTL interface on separate I/O;
- 1.8 VDD;
- slow down mode;
- late and double late write modes;
- pipelined read mode;
- echo clocks;
- programmable output drive strength;
- byte-write operation;
- programmable chip enables;
- IEEE 1149.1 JTAG boundary-scan testability;
- and 209-pin BGA package
More information on the SigmaRAM Consortium and its associated members can be obtained by accessing
www.sigmaram.com.
SigmaRAM is a trademark of the SigmaRAM Consortium. All other companies of products referenced herein
are trademarks or registered trademarks of their respective holders.
