| What is SigmaRAM? |
|
SigmaRAM SRAM devices are the industry's first comprehensive, standardized
family of high-speed synchronous SRAMs developed specifically for networking and telecommunications applications. They
live up to their name (Sigma is the mathematical symbol for "summation") by consolidating many different architectures
and modes of operation into a single product family. Developed by the SigmaRAM Consortium, these SRAMs provide the most
flexible and highest-performance networking and telecommunication memory solutions available in the SRAM industry
today.
|
| What is the charter of the SigmaRAM Consortium? |
|
The SigmaRAM Consortium is an industry group of five leading SRAM companies
who joined together to set open standards for a new breed of synchronous SRAMs targeted specifically for the networking
and telecommunications markets. Spearheading the movement toward open standards, the consortium succeeded in developing
the first comprehensive family of networking SRAM standards that has been approved by JEDEC. The open standard provides
all SRAM manufacturers the opportunity to develop compatible devices.
|
Who are the members
of the SigmaRAM
Consortium? |
|
Members of the SigmaRAM Consortium include GSI Technology, Integrated
Silicon Solution Inc., Mitsubishi Electric Corporation, Sony Electronics Inc. and Toshiba Corporation.
|
| Why is there a need for SigmaRAM SRAMs? |
|
The explosion in communication technology, service, and bandwidth has led
to a dramatic increase in the performance requirements and complexity of network components, including memory.
Originally, packet speeds within a network were slow enough that off-the-shelf memory devices such as Burst SRAMs were
more than adequate to handle the load. Today, network elements require significantly higher memory throughput in order to operate at
10Gb/s (OC-192) levels and above. Moreover, with enhanced service expectations, multiple protocol translations, and new
QoS requirements, the burden of switching and routing elements has greatly increased. Consequently, off-the-shelf
memory devices are no longer adequate to the task. SigmaRAM devices are designed specifically to meet these
requirements.
|
What is the target market
for SigmaRAM devices? |
|
The standardized SRAMs are targeted primarily at the high-speed networking
and telecommunications markets.
|
| What applications are the SigmaRAM SRAM devices designed for? |
|
SigmaRAM devices are designed to support the needs of high-speed networking
and telecommunications applications that require high data throughput, such as buffering, classification, and
routing.
|
Are there other companies
or groups that have similar
SRAM
architectures or
products? |
|
Yes, but those products are not consolidated into a single scalable
packaging solution and are not at the performance levels offered by the initial SigmaRAM devices. The SigmaRAM family
of SRAMs is unique in both respects.
|
What are the key benefits of SigmaRAM SRAM device
that differentiate
them from
competitors? |
|
The SigmaRAM family is the first open high-speed synchronous SRAM standard
targeted specifically for the networking and telecommunications markets. Unlike existing solutions, the SigmaRAM product
standard is highly scalable — the package and pinouts have been defined to support SRAM densities up to 144Mb.
Functionally, SigmaRAM devices are capable of sustaining an unprecedented data throughput of up to 24Gb/s during
completely random addressing at 333MHz. And, because the SigmaRAM family supports a variety of architectures and
modes of operation, each designed to optimize a specific sequence of read and write operations, it will quickly become
the most comprehensive SRAM solution available in the industry.
Other key benefits that differentiate SigmaRAM devices include programmability; wide bus widths; low power and the need
for only a single clock.
|
What are the features of
the SigmaRAM family of
SRAMs?
| |
SigmaRAM devices feature superior clock rates (up to 333 MHz), wide data
buses (from x18 to x72), common and separate data buses, single and double data rate operation, a source-synchronous
interface (via Echo Clocks), and low power (by utilizing a 1.8V supply voltage). This combination of features gives the
SigmaRAM family industry-leading performance.
Other features include a 209-pin BGA package that provides twin benefits of scalability and ease in routing over
traditional workstation/server packaging; programmable chip enables for easy depth expansion; programmable output drive
strength; late and double late write modes; pipeline read mode; coherent reads and writes; byte-write operation; IEEE
1149.1 JTAG boundary-scan testability; clamshell pinouts; burst mode; and 24Gb/s throughput.
|
When will SigmaRAM
SRAMs be available? |
|
Consortium members will begin sampling 18Mb SigmaRAM devices in Q4 2001.
Common I/O versions will be available first, followed shortly thereafter by separate I/O versions.
|
| Will all versions be available from all vendors? |
|
Most consortium members have agreed to offer a mixture of common and
separate I/O versions as a minimum. However, each of the member companies will independently decide on the part numbers
that it will manufacture.
|
| How much will these SRAMs cost? |
|
SigmaRAM devices will be priced competitively as determined by the market.
Please refer to individual company representatives for price quotes.
|
| Why should anyone consider using a larger 209-pin BGA package as opposed
to the existing 165-pin BGA package? |
|
Although the 209-pin BGA package is larger than the 165-pin BGA package, it
provides advantages in scalability and feature set that outweigh its size disadvantage. The SigmaRAM Consortium chose the
209-pin BGA package because it will accommodate 18Mb, 36Mb, 72Mb, and 144Mb SRAM densities as the process technology
for each density becomes available. The same cannot be said for the 165-pin BGA package. While it can accommodate 18Mb
SRAM density manufactured with existing process technology, it will not be able to accommodate 36Mb SRAM density
manufactured with the next-generation process technology. Therefore, one 209-pin BGA package containing a single 36Mb
SRAM will actually occupy less board space than two 165-pin BGA packages each containing a single 18Mb SRAM.
Also, the additional pins available in the 209-pin BGA package allow SigmaRAM SRAMs to offer important features such
as programmable chip enables, echo clock pairs on each side of the chip and user programmable operating
modes.
|
Do SigmaRAM SRAM
devices have Double Data
Rate parts? |
|
Yes. Both the common I/O and separate I/O SigmaRAM devices offer Double
Data Rate architectures.
|
| Where can I get more information on SigmaRAM SRAMs? |
|
Detailed roadmaps, data sheets and information are now available at the
consortiumÕs website, www.SigmaRAM.com. |
