SigmaRAM™ Consortium Announces 24-Gb/s, 18-Mbit,
333-MHz Synchronous SRAM Product Family
for Networking and Telecom Markets
SAN JOSE, Calif. - June 18, 2001 - The SigmaRAM™ Consortium today announced a comprehensive multiyear
product roadmap, datasheets, and first availability of JEDEC-standard high-speed 18-Mbit synchronous SRAMs that can
sustain an unprecedented data throughput rate of up to 24 gigabits per second (Gb/s) at a 333-MHz clock speed.
Consortium members participating in the SigmaRAM industry roadmap include GSI Technology, Integrated Silicon Solution
Inc., Mitsubishi Electric Corporation, Sony Electronics Inc., and Toshiba Corporation. Members of the SigmaRAM
Consortium have agreed on what they believe to be the industryÕs first and only open-standard for multiple-sourced,
high-speed synchronous SRAMs tailored to the networking and telecom markets (the SigmaRAM devices). The members of the
consortium intend to independently develop and market products adhering to this standard.
To demonstrate the viability of SigmaRAM devices for networking and telecom uses, the consortium has worked closely
with Xilinx, Inc., to recently interface the SigmaRAM devices with the Xilinx® Virtex®-II platform FPGA
(field programmable gate array), using the system I/O features of this component and the timing capabilities of both
devices. "This new interface enables the designer to take full advantage of both the high-speed and data alignment
capabilities of the Virtex-II I/Os while implementing all access protocol functions," said Jean-Louis Brelet, manager,
applications engineering, Xilinx Advanced Products Group.
"For the last decade, the SRAM market has been dominated by cache memory applications," said Bob Merritt, vice
president, Semico Research, an analyst with expertise in networking and PC architectures. "However today, networking
and communications have clearly replaced PCs as the main drivers for new concepts and technologies. SRAMs are now
required to deliver much higher densities, lower power consumption, easier PC board routing, and new SRAM interface
protocols for networking."
"SigmaRAM supports the wide bus structures and fast random-address cycle times that traditional SRAMs cannot handle
effectively," added Merritt. "The full support of the SigmaRAM Consortium will go far in assuring customers of a solid
supply of material and a strong roadmap to future products."
SigmaRAM devices consolidate many different SRAM architectures and operation modes into a single product family for
industry-leading performance and design flexibility. SigmaRAM devices come in two architectures - common I/O and
separate I/O. These devices offer the widest data bus of 72 bits in the common I/O single data rate (SDR)
architecture, and are the first to offer 36 bits in the separate I/O architecture. SigmaRAM devices operating at 333MHz
are capable of sustaining up to 24Gb/s data throughput with entirely random addressing. Common I/O versions share
one data bus, yet incur no penalty when alternating between reads and writes. Separate I/O versions feature
independently optimized read and write buses. Both variations offer double data rate (DDR) architectures that can
sustain similar throughput with fewer pins.
SigmaRAM devices use a 209-pin, ball grid array (BGA) package that provides twin benefits of scalability from 18-Mbit
to 144-Mbit densities and ease in routing over traditional SRAM packaging for workstation and server applications.
Additional features of SigmaRAM devices include low-power consumption resulting from a 1.8-volt supply voltage and
JEDEC-standard 1.5- and 1.8-volt interfaces, a source-synchronous interface (via echo clocks), programmable chip
enables for easy depth expansion, programmable output drive strength, late and double late write modes, pipeline read
mode, coherent reads and writes, byte-write operation, IEEE 1149.1 JTAG boundary-scan testability, clamshell pinouts,
and burst mode.
SigmaRAM device product roadmaps and datasheets are available on the SigmaRAM Consortium website at www.sigmaram.com.
Availability
SigmaRAM Consortium members expect to begin sampling 18-Mbit SigmaRAM devices in the fourth quarter of 2001. Common
I/O versions will be available first, followed shortly thereafter by separate I/O versions. Volume production of
common I/O and separate I/O architecture versions of SigmaRAM devices are expected to begin in the first quarter of
2002.
About the SigmaRAM Consortium
Founded in July 1999, the SigmaRAM Consortium is an industry group of leading SRAM suppliers who joined together to set
open standards for a new breed of synchronous SRAM targeted primarily at the networking and telecom markets. The
consortium has succeeded in developing the first and only comprehensive family of networking SRAM standards approved by
JEDEC. As the mathematical symbol "sigma" represents "summation," SigmaRAM devices are the "summation" of many
different architectures and modes of operation into a single product family. These high-speed synchronous SRAMs
provide the most flexible and highest performance networking and telecom memory solutions available in the SRAM
industry today. For more information on the SigmaRAM Consortium, please visit
www.sigmaram.com.
Trademark Information
SigmaRAM is a trademark of the SigmaRAM Consortium. Xilinx and Virtex are registered trademarks of Xilinx, Inc. All
other companies and products referenced herein are trademarks or registered trademarks of their respective holders.
Editorial Contacts:
GSI Technology
David Chapman
(512) 345-6435
dchapman@gsitechnology.com |
|
Sony Electronics Inc.
Natalie Kessler, The Hoffman Agency
(for Sony Electronics
Inc.)
(408) 975-3032
nkessler@hoffman.com
|
Integrated Silicon Solutions Inc.
Stephen Lau
(408)
969-4717
stephen_lau@issi.com |
|
Toshiba Corporation
Michelle Schneider
(949)
455-2000
michelle.schneider@taec.toshiba.com
|
Mitsubishi Electric Corporation
John Garner
(408)
774-3191
garner_john@edg.mea.com |
|
SigmaRAM Consortium Members |
SigmaRAM Fact Sheet |
SigmaRAM Frequently Asked Questions
